Traditionally, wafer fabrication completed semiconductor devices in wafer form are probed, binned, singulated into discrete die, packaged, and then final package tested (final test). Many IC products have full probe test coverage with an extensive set of parametric tests including high complexity and high performance test parameters, including both DC parametric testing and AC parametric testing because the probe system has a low stepping time and is cheaper to operate as compared to a package test system. As used herein and used in the art, the term “parametric test” means the measurement and verification of terminal voltage and current characteristics at one or more device pins or pads of a semiconductor device. Moreover, with the wafer form, there is no jamming, relatively easy electrical contact, and the ability to generally handle large lot sizes.
Final package test (final test) is costly due to use of an expensive commercial tester and a handler. Final test is also device specific, which generally means an individual such as a technician has to reconfigure the setup (e.g., change to a new contactor) for the next device to be final tested. Final test is known to cause poor Overall Equipment Efficiency (OEE) that drives high final test cost, such as an OEE of about 30% to 40%, and can take about 1 sec per unit to complete the tests.
One known approach to reducing the final test cost is using a streamlined final test routine including a reduced number of parametric tests compared to the parametric tests performed at wafer probe. This means the high complexity and performance test parameters are performed only probe, so the streamlined final test routine does not repeat these tests. However, in the case of parametric shifts of the IC die between probe and the streamlined final test routine which includes assembly, since the high complexity and high performance test parameters are not performed in the streamlined approach, test escapes happen which are known to sometimes adversely impact product quality levels.